1. Field of the Invention
The present invention relates to an input transition detection circuit for detecting when a signal input to a zero-power part switches states, the input transition detection circuit then providing a signal to wake up the zero-power part from a low power mode. More particularly, the present invention relates to circuitry for implementing an input transition detection circuit which can be utilized in a zero-power programmable logic device (PLD).
2. Description-of the Prior Art
Electronic circuits in battery powered devices such as notebook computers need to utilize as little power as possible to preserve the batteries for an extended period of time. Even with devices which are not battery powered, it is desirable to have electronic circuits which operate with as little power consumption as possible to conserve energy, thus reducing operational costs.
More recently manufacturers have developed specialized electronic parts, called zero-power parts, for use in battery powered devices such as notebook computers. The zero-power parts have a low power consumption mode, also referred to as a sleep or standby mode, which is entered when the zero-power part has not been accessed for a period of time. During the sleep or standby mode, every circuit in the zero-power part will be turned off, only to be turned back on, or waked up, after an input transition signal is received.
An input transition detection circuit is utilized on the zero-power part to detect any input switching and send a signal to wake up, or power up, a part from a low power mode. The signal provided by the input transition detection circuit is a time delay signal enabling the zero-power part to reenter a sleep mode after the time delay.
An example of a zero-power part currently available is the AmPALCE22V10Z-25, a programmable array logic (PAL) device, a type of PLD, manufactured by Advanced Micro Devices, Inc. The AmPALCE22V10Z-25 is also available in a non zero-power version which provides faster operational speeds since the part does not require time to be powered up from a sleep mode.
FIG. 1 is a block diagram showing components of the AmPALCE22V10Z-25. The AmPALCE22V10Z-25 has an input port labeled I, ten ports which can be configured to be input or output ports labeled I/O, and a port which can be configured to be a clock or an input port labeled CK/I. The ports, when configured as input ports, receive and transmit an input signal to an input buffer of the input buffers labeled 100(a-l). The input buffers enable the AmPALCE22V10Z-25 to be compatible with external circuitry and provide both true and complement outputs. The true and complement outputs provided by the input buffers are received by circuitry functioning as a programmable AND array 102 which drives an OR array 104(a-j) to provide a sum of products term. The outputs from the OR array are provided to output logic macrocells 106 which provide outputs which are programmable to be registered or combinatorial. The outputs from the output logic macrocells are provided to output buffers 108 to be supplied to circuitry external to the AmPALCE22V10Z-25.
In PLDs, such as the AmPALCE22V10Z-25 shown in FIG. 1, every port configurable to be an input port will require an input transition detection circuit to implement a zero-power part.
FIG. 2 shows components of an input transition detection circuit 200 utilized for each port configurable to be an input port on the AmPALCE22V10Z-25. Also shown in FIG. 2 are connections for the input transition detection circuit 200 to an input buffer 202, similar to input buffers 100(a-l) of FIG. 1. Input buffer 202 includes inverters 204, 206 and 208 coupled in series to receive an input signal at a port labeled IN. Inverters 204, 206 and 208 include p-channel pull up transistors with increasingly larger sizes from inverter 204 to inverter 208 and n-channel pull down transistors with decreasingly smaller sizes from inverter 204 to inverter 208. Inverters 204 through 208 have transistors sized to increase power to drive a high capacitance load. Input buffer 202 additionally includes an inverter 210 which is connected to the output of inverter 208 to provide the true output labeled ROW to the programmable AND array 102 of FIG. 1. Also included is an inverter 212 which is connected to the input of inverter 208 to provide the complement output labeled ROWB to the programmable AND array 102 of FIG. 1.
The input transition detection circuit 200 includes two inverters 220 and 222 and nine transistors including six transistors 226, 228, 230, 232, 234 and 236 along with three transistors which make up inverter 224. The circles on transistors, such as 230 and 232, indicate a P-channel transistor, while transistors without the circles are N-channel transistors.
In the input transition detection circuit 200, inverters 220 and 222 are coupled in series from the output of inverter 208 to the source of transistor 226. The drain of transistor 226 is coupled to the gate of transistor 234 at a node 253. The drain of transistor 234 provides a time delay signal (TDS) node to output a time delay signal used to control a low power mode. The source of transistor 234 is connected to the drain of transistor 236 which has its source connected to ground. The output of inverter 220 is connected to the source of transistor 228. The drain of transistor 228 is coupled to the gate of transistor 236 at a node 254. The gates of transistors 226 and 228 are coupled to a system power supply.
Inverter 224 is connected from the output of inverter 204 of input buffer 202 to the gate of transistor 230. The drain of transistor 230 is connected to the gate of transistor 234 at node 253 while the source is connected to the system power supply. The output of inverter 204 is also connected to the gate of transistor 232. The drain of transistor 232 is connected to the gate of transistor 236 at node 254 while the source is connected to the system power supply.
In operation, we begin by assuming an input signal at node IN is high. With node IN high, the output of inverter 204 will be low turning on transistor 232 to pull node 254 high. Transistor 236, having a gate connected to node 254, will thus be on. Note that transistors 230 and 232 are sized to draw more current than transistors 226 and 228 so that if either transistors 230 or 232 are on, they will override transistors 226 and 228.
Meanwhile, with the output of inverter 204 being low, the output of inverter 206 will be high, the output of inverter 208 will be low, and the output of inverter 220 will be high making the output of inverter 222 low. With the output of inverter 222 being low, node 253 will go to low since transistor 226 is on. Since the output of inverter 204 is low, the output of inverter 224 will be high turning off transistor 230 so that transistor 226 will not be overridden. Transistor 234, having a gate connected to node 253, will be off. With one of the two series transistors 234 and 236 off, there will be no path to ground for node TDS, so node TDS will remain high.
When IN switches from high to low, the output of inverter 204 will go high making the output of inverter 224 low and turning on transistor 230 to pull node 253 high. At this point, both transistors 234 and 236 will be on pulling node TDS to low indicating an input transition detection. With the output of inverter 204 being high, the output of inverter 206 will be pulled low, and the output of inverter 208 will be pulled high pulling the output of inverter 220 low to slowly discharge node 254 through small transistor 228. After a time delay when node 254 has discharged, transistor 236 will turn off, and node TDS will return to high. When IN switches from low to high, the output of inverter 204 will go low turning on transistor 232 to pull node 254 high and turn on transistor 236. With both transistors 234 and 236 now on, node TDS will be pulled low, starting another input transition detection indication. With the output of inverter 206 going high, the output of inverter 208 will go low, and the output of inverter 220 will go high making the output of inverter 222 low and slowly discharging node 253. After a time delay when node 253 has discharged, transistor 234 will turn off, and node TDS will return to high.
In a typical zero-power part, the TDS nodes of the input transition detection circuits for each input buffer of a part are connected together. With the circuitry of FIG. 2, a TDS signal will remain low for a period of approximately 5 nanoseconds after an input transition is detected. A separate circuit, not shown, connected to the TDS nodes provides a signal for transitioning the part into a sleep mode if all TDS signals remain off for a period of approximately 50 nanoseconds.
Thus, as shown in FIG. 3, with an input signal 300, TDS signals 302 of approximately a 5 nanosecond duration will be generated which are used to wake up a part if the part is in a sleep mode. If no input signal transition occurs within 50 nanoseconds, a signal 304 will be generated to transition the part back into a sleep mode.
The performance of an input transition detection circuit is measured by how quickly the input transition detection circuitry can send a wake-up signal after an input transition occurs. Further, because of the number of inputs available on a part, for example 12 on the AmPALCE22V10Z-25, the number of components which make up the input transition detection circuitry should be limited to limit the amount of chip area required for the input transition detection circuitry and to reduce manufacturing costs.